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1nv/hz low noise 210c instrumentation amplifier AD8229 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features designed for 210c operation low noise 1 nv/hz input noise 45 nv/hz output noise high cmrr 126 db cmrr (minimum), g = 100 80 db cmrr (minimum) to 5 khz, g = 1 excellent ac specifications 15 mhz bandwidth (g = 1) 1.2 mhz bandwidth (g = 100) 22 v/s slew rate thd: 130 db (1 khz, g = 1) versatile 4 v to 17 v dual supply gain set with single resistor (g = 1 to 1000) temperature range: ?40c to +210c applications down-hole instrumentation harsh environment data acquisition exhaust gas measurements vibration analysis general description the AD8229 is an ultralow noise instrumentation amplifier designed for measuring small signals in the presence of large common-mode voltages and high temperatures. the AD8229 has been designed for high temperature operation. the process is dielectrically isolated to avoid leakage currents at high temperatures. the design architecture was chosen to compensate for the low v be voltages at high temperatures. to enhance long term reliability, the wire bonding in the packaging is designed to avoid intermetallic absorption at high temperatures. the AD8229 excels at distinguishing tiny signals. it delivers industry leading 1 nv/hz input noise performance. the AD8229s high cmrr prevents unwanted signals from corrupting the acquisition. the cmrr increases as the gain increases, offering high rejection when it is most needed. functional block diagram top view (not to scale) ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 AD8229 09412-001 figure 1. 100 80 60 40 20 0 ?20 ?40 ?60 ?80 ?100 v osi ( v) ?55 ?35 ?15 5 25 45 65 85 105 125 145 165 185 205 225 temperature (c) 09412-016 figure 2. typical input offset vs. temperature (g = 100) the AD8229 is one of the fastest instrumentation amplifiers available. its current feedback architecture provides bandwidth that is quite high, even at high gains, for example, 1.2 mhz at g = 100. with the high bandwidth comes excellent distortion performance, allowing use in demanding applications such as vibration analysis. gain is set from 1 to 1000 with a single resistor. a reference pin allows the user to offset the output voltage. this feature is useful when interfacing with analog-to-digital converters. the AD8229 is available in an 8-pin ceramic dip package.
AD8229 rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 6 ? thermal resistance ...................................................................... 6 ? esd caution .................................................................................. 6 ? pin configuration and function descriptions ............................. 7 ? typical performance characteristics ............................................. 8 ? theory of operation ...................................................................... 17 ? architecture ................................................................................ 17 ? gain selection ............................................................................. 17 ? reference terminal .................................................................... 17 ? input voltage range ................................................................... 18 ? layout .......................................................................................... 18 ? input bias current return path ............................................... 19 ? input protection ......................................................................... 19 ? radio frequency interference (rfi) ........................................ 19 ? calculating the noise of the input stage ................................. 20 ? outline dimensions ....................................................................... 21 ? ordering guide .......................................................................... 21 ? revision history 1/11revision 0: initial version
AD8229 rev. 0 | page 3 of 24 specifications + v s = 15 v, ? v s = ? 1 5 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k , unless otherwise noted. table 1 . dip package parameter test conditions min typ max unit common - mode rejection ratio (cmrr) cmrr dc to 60 hz with 1 k source imbalanc e v cm = 10 v g = 1 86 db temperature drift t a = ?40 c to + 210c 300 nv/v/ c g = 10 106 db temperature drift t a = ?40 c to + 210c 30 nv/v/ c g = 100 126 db temperature drift t a = ?40 c to + 210c 3 nv/v/ c g = 1000 t a = ?40 c to + 210c 134 db cmrr at 5 khz v cm = 10 v g = 1 80 db g = 10 90 db g = 100 90 db g = 1000 90 db voltage noise v in +, v in ? = 0 v spectral density 1 : 1 khz input voltage noise, e ni 1 1.1 nv/ hz output voltage noise, e no 45 5 0 nv/ hz peak to peak: 0.1 hz to 10 hz g = 1 2 v p -p g = 1000 100 nv p -p current noise spectral density: 1 khz 1.5 pa/ hz peak to peak: 0.1 hz to 10 hz 100 pa p -p voltage offset v os = v osi + v oso /g input offset, v osi 100 v average tc ?40 c to + 210c 0.1 1 v/c output offset, v oso 1000 v average tc ?40 c to + 210c 3 10 v/c offset rti vs. supply (psr) v s = 5 v to 15 v g = 1 ?40 c to + 210c 86 db g = 10 ?40 c to + 210c 106 db g = 100 ?40 c to + 2 10c 126 db g = 1000 ?40 c to + 210c 130 db input current input bias current 70 na high temperature t a = 210 c 200 na input offset current 35 na high temperature t a = 210 c 50 na
AD8229 rev. 0 | page 4 of 24 dip package parameter test conditions min typ max unit dynamic response small signal bandwidth C 3 d b g = 1 15 mhz g = 10 4 mhz g = 100 1 .2 mhz g = 1000 0.15 mhz settling time 0.01% 10 v step g = 1 0. 75 s g = 10 0. 65 s g = 100 0.85 s g = 1000 5 s settling time 0.001% 10 v step g = 1 0.9 s g = 10 0. 9 s g = 100 1. 2 s g = 1000 7 s slew rate g = 1 to 100 2 2 v/s gain 2 g = 1 + (6 k /r g ) gain range 1 1000 v/v gain error v out = 10 v g = 1 0.01 0.03 % g = 10 0.05 0.3 % g = 100 0.05 0.3 % g = 1000 0.1 0.3 % gain nonlinearity v out = ?10 v to +10 v g = 1 to 1000 r l = 10 k 2 ppm gain vs. temperature g = 1 ?40 c to + 210c 2 5 ppm/c g > 10 ?40 c to + 210c ?100 ppm/c input impedance (pin to ground) 3 1 .5||3 g ||pf input operating voltage range 4 v s = 5 v to 18 v for dual supplies ?v s + 2.8 +v s ? 2.5 v over temperature ?40 c to + 210 c ?v s + 2.8 +v s ? 2.5 v output output swing r l = 2 k ?v s + 1.9 +vs ? 1.5 v high temperature t a = 210 c ?v s + 1.1 +vs ? 1.1 v output swing r l = 10 k ?v s + 1.8 +vs ? 1.2 v high temperature t a = 210 c ?v s + 1.1 +vs ? 1.1 v short - circuit curr ent 35 ma reference input r in 10 k i in v in +, v in ? = 0 v 70 a voltage range ?v s +v s v reference gain to output 1 v/v reference gain error 0. 01 %
AD8229 rev. 0 | page 5 of 24 dip package parameter test conditions min typ max unit power supply operating range 4 17 v quiescent current 6.7 7 ma high temperature t = 210c 12 ma temperature range for specified performance 5 ?40 +210 c 1 total v oltage noise = (e ni 2 + (e no /g) 2 )+ e rg 2 ) . see the theory of operation section for more information. 2 these specifications do not include the tolerance of the exter nal gain setting resistor , r g . for g>1, r g errors should be added to the speci fications given in this table. 3 differential and common - mode input impedance can be calculated from the pin impedance: z diff = 2(z pin ); z cm = z pin /2. 4 input voltage range of the AD8229 input stage only. the i nput range can de pend on the common - mode voltage, differential voltage, gain , and reference voltage. see the input voltage range section for more details. 5 performance at 210 c is guaranteed for 1000 hours.
AD8229 rev. 0 | page 6 of 24 absolute maximum rat ings table 2 . parameter rating supply voltage 1 7 v output short - circuit current duration indefinite max imum v oltage at C in, +in 1 v s differential input voltage 1 gain 4 4 > gain > 50 gain 50 v s 50 v/gain 1 v maximum voltage at ref v s storage temperature range c er dip ?65c to + 1 50c specified temperature range c er dip ?40c to +210c maximum junc tion temperature c er dip 245c 1 for voltages beyond these limits , use input protection resistors . see the a pplications section for more information. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. thi s is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may af fect device reliability. thermal resistance ja is specified for a device in free air. table 3 . package ja unit 8 - lead , size brazed, cer dip , 4 - layer jedec board 100 c/w esd caution
AD8229 rev. 0 | page 7 of 24 pin configuration an d function desc riptions top view (not to scale) ?in 1 r g 2 r g 3 +in 4 +v s 8 v out 7 ref 6 ?v s 5 AD8229 09412-003 figure 3 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 ?in negative input terminal . 2, 3 r g gain setting terminals. place resistor a cross the r g p ins to s et the gain. g = 1 + (6 k /r g ) . 4 +in positive input ter minal . 5 ?v s negative power supply terminal . 6 ref reference voltage terminal. d rive t his t er minal with a l ow impedance voltage s ource to l evel - shift the o utput . 7 v out output terminal . 8 +v s po sitive power supply terminal .
AD8229 rev. 0 | page 8 of 24 typical performance characteristics t = 25c, v s = 15, v ref = 0, r l = 2 k ?, unless otherwise noted. 60 50 40 30 20 10 0 ?60 ?40 ?20 20 0 v osi 15v ( v) hits 40 60 n: 200 mean: 12.2 : 8.2 09412-004 figure 4 . typical distribution of input offset voltage v oso 15v ( v) hits 35 30 20 25 15 5 10 0 800 ?600 ?400 ?200 0 200 400 600 n: 200 mean: 0.9 : 161.2 09412-005 figure 5. typical distribution of out put offset voltage 40 35 30 20 25 15 5 10 0 ?50 ?40 ?20 ?10 ?30 10 0 i bias ( na ) hits 20 30 inverting noninverting n: 200 mean: ?6.1 : 6.7 n: 200 mean: ?10.1 : 6.9 09412-006 figure 6 . typical distribution of input bias current i bias offset ( na ) hits n: 201 mean: 4.0 : 0.7 60 50 30 40 20 10 0 0 2 4 6 8 09412-007 figure 7 . typical distribution of input offset current hits ?40 ?60 ?20 0 20 40 60 20 0 40 60 80 100 120 cmrr g1 ( v/v) n: 200 mean: 10.9 : 3.7 09412-008 figure 8. typi cal distribution of common mode rejection, g = 1 hits 09412-015 ?60 ?40 ?20 0 20 0 5 10 15 20 25 30 35 n inv g error g1 10k 15v ( v/v) n: 198 mean: ?9.1 : 9.9 figure 9 . typical distribution of gain error, g = 1
AD8229 rev. 0 | page 9 of 24 ?3 ?2 ?1 0 1 2 3 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 common-mode vo lt age (v) output vo lt age (v) g = 1, v s = 5v 25c 210c 09412-009 figure 10 . input common - mode voltage vs. output voltage, dual supply, v s = 5 v; g = 1 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 output vo lt age (v) common-mode vo lt age (v) g = 1, v s = 12v 25c 210c 09412-010 figur e 11 . input common - mode voltage vs. output voltage, dual supply , v s = 12 v; g = 1 ?14 ?10 ?6 ?12 ?8 ?4 ?2 0 2 4 6 10 8 12 14 ?15 ?10 ?5 0 5 10 15 output vo lt age (v) common-mode vo lt age (v) g = 1, v s = 15v 25c 210c 09412-0 1 1 figure 12 . input common - mode voltage vs. output voltage, dual supply , v s = 15 v; g = 1 ?3 ?2 ?1 0 1 2 3 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 common-mode vo lt age (v) output vo lt age (v) g = 100, v s = 5v 25c 210c 09412-012 figure 13 . input common - mode voltage vs. output voltage, dual supply, v s = 5 v; g = 100 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 output vo lt age (v) common-mode vo lt age (v) g = 100, v s = 12v 25c 210c 09412-013 figure 14 . input common - mode voltage vs. output voltage, dual supply , v s = 12 v; g = 100 ?14 ?10 ?6 ?12 ?8 ?4 ?2 0 2 4 6 10 8 12 14 ?15 ?10 ?5 0 5 10 15 output vo lt age (v) common-mode vo lt age (v) g = 100, v s = 15v 25c 210c 09412-014 figure 15 . input common - mode voltage vs. output voltage, dual supply , v s = 15 v; g = 100
AD8229 rev. 0 | page 10 of 24 ?12.28v 12.60v ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 input bias current (na) common-mode vo lt age (v) 09412-068 figure 16 . input bias current vs. common - mode voltage frequenc y (hz) 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k 1m 09412-069 neg a tive psrr gain = 1 gain = 1000 gain = 10 gain = 100 figure 17 . positive psr r vs. frequency frequenc y (hz) 0 20 40 60 80 100 120 140 neg a tive psrr 160 1 10 100 1k 10k 100k 1m 09412-070 gain = 1 gain = 1000 gain = 10 gain = 100 figure 18 . negative p srr vs . frequency ?30 ?20 ?10 0 10 20 30 40 50 60 70 100 1k 10k 100k 1m 10m 100m gain (db) frequenc y (hz) gain = 1 gain = 1000 gain = 100 gain = 10 v s = 15v 09412-017 figur e 19 . gain vs. frequency 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) gain = 1 gain = 1000 gain = 10 gain = 100 bandwidth limited 09412-018 figure 20 . cmrr vs. frequency 0 20 40 60 80 100 120 140 160 1 10 100 1k 10k 100k 1m cmrr (db) frequenc y (hz) gain = 1 gain = 1000 gain = 10 gain = 100 bandwidth limited 09412-019 figure 21 . cmrr vs. frequency , 1 k source imbalance
AD8229 rev. 0 | page 11 of 24 0 2 4 6 8 10 12 0 100 200 300 400 500 600 700 change in input offset vo lt age ( v) w arm-u p time (s) 09412-071 figure 22 . change in input offset voltage (v osi ) vs. warm - up time ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?200 ?150 ?100 ?50 0 50 100 150 200 ?55 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 140 155 170 185 200 215 230 input offset current (na) input bias current (na) temper a ture (c) input offset current input bias current 09412-072 figure 23 . input bias current and input offset current vs. temperature ?250 ?200 ?150 ?100 ?50 0 50 100 150 gain error (v/v) 09412-073 ?55 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 140 155 170 185 200 215 230 temper a ture (c) figure 24 . gain error vs. temperature , g = 1, normalized at 25 c ?10 ?5 0 5 10 15 20 ?55 ?40 ?25 ?10 ?5 20 35 50 65 80 95 110 125 140 155 170 185 200 215 230 cmrr (v/v) temper a ture (c) 09412-023 figure 25 . cmr r vs. temperature , g = 1, normalized at 25 c 0 2 4 6 8 10 12 ?55 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 140 155 170 185 200 215 230 supp l y current (ma) temper a ture (c) 09412-074 figure 26 . supply current vs. temperature , g = 1 ?50 ?40 ?30 ?20 ?10 0 10 20 30 40 50 short circuit current (ma) i short? i short+ ?55 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 140 155 170 185 200 215 230 temper a ture (c) 09412-075 figure 27 . short - circuit current vs. temperature , g = 1
AD8229 rev. 0 | page 12 of 24 +sr ?sr 0 5 10 15 20 25 30 slew r a te (v/s) ?55 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 140 155 170 185 200 215 230 temper a ture (c) 09412-076 figure 28 . slew rate vs. temperature , v s = 15 v, g = 1 +sr ?sr 0 5 10 15 20 25 slew r a te (v/s) ?55 ?40 ?25 ?10 5 20 35 50 65 80 95 1 10 125 140 155 170 185 200 215 230 temperature (c) 09412-077 figure 29 . slew rate vs. temperature , v s = 5 v, g = 1 4 6 8 10 12 14 16 18 input vo lt age (v) referred t o supp l y vo lt ages supp l y vo lt age (v s ) ?55c ?40c +25c +85c +125c +150c +210c +225c +v s ?v s ?1.0 ?2.0 +1.0 +2.0 +2.5 ?0.5 ?1.5 ?2.5 +1.5 +1.5 09412-028 figure 30 . input voltage limit vs. supply voltage 4 6 8 10 12 14 16 18 output vo lt age swing (v) referred t o supp l y vo lt ages supp l y vo lt age (v s ) ?55c ?40c +25c +85c +125c +150c +210c +225c +v s ?v s ?0.8 +0.8 +1.6 +2.0 ?0.4 ?1.2 +1.2 +0.4 09412-029 figure 31 . output voltage swing vs. supply voltage, r l = 10 k 4 6 8 10 12 14 16 18 output vo lt age swing (v) referred t o supp l y vo lt ages supp l y vo lt age (v s ) ?55c ?40c +25c +85c +125c +150c +210c +225c +v s ?v s ?0.8 +0.8 +1.6 +2.0 ?0.4 ?1.2 +1.2 +0.4 09412-030 figure 32 . output voltage swing vs. supply voltage, r l = 2 k ?15 ?10 ?5 0 5 10 15 100 1k 10k 100k output vo lt age swing (v) load () ?55c ?40c +25c +85c +125c +150c +210c +225c v s = 15v 09412-031 figure 33 . output voltage swing vs. load resistance
AD8229 rev. 0 | page 13 of 24 10 100 1m 5m output voltage swing (v) referred to supply voltages output current (a) +v s ?v s +0.4 ?0.4 ?0.8 ?1.2 +0.8 +1.2 +1.6 ?1.6 v s = 15v +1.8 ?55c ?40c +25c +85c +125c +150c +210c +225c 09412-032 figure 34 . output voltage swing vs. output current ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearit y (ppm/div) output vo lt age (v) gain = 1 09412-083 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 figure 35 . gain nonlinearity, g = 1, r l = 10 k ?10 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 nonlinearit y (ppm/div) output vo lt age (v) gain = 1000 09412-084 figure 36 . ga in nonlinearity, g = 100 0, r l = 10 k 0.1 1 10 100 1000 1 10 100 1k 10k 100k noise (nv/ hz) frequenc y (hz) gain = 1 gain = 1000 gain = 10 gain = 100 09412-037 figure 37 . voltage noise spectral density vs. frequency 1s/div gain = 1000, 100nv/div gain = 1, 2v/div 09412-086 figure 38 . 0.1 hz to 10 hz rti voltage noise, g = 1, g = 1000 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 1 10 100 1k 10k 100k noise (pa/ hz) frequenc y (hz) 09412-087 figure 39 . cu rrent noise spectral density vs. frequency
AD8229 rev. 0 | page 14 of 24 50pa/div 1s/div 09412-088 figure 40 . 1 hz to 10 hz current noise 0 5 10 15 20 25 30 100 1k 10k 100k 1m 10m output vo lt age (v p-p) frequenc y (hz) g = 1 v s = 15v v s = 5v 09412-089 figure 41 . large signal frequency response 5v/div 0.002%/div 750ns to 0.01% 872ns to 0.001% time ( s) 2 s/div 09412-090 figure 42 . large signal pulse response and settling time (g = 1), 10 v step, v s = 15 v 5v/div 2 s/div 640ns to 0.01% 896ns to 0.001% time ( s) 0.002%/div 09412-091 figure 43 . large signal pulse response and settling time (g = 10), 10 v step, v s = 15 v 50mv/div 50mv/div 1s/div 09412-048 g = 1 25c 175c 210c 225c figure 44 . small signal response, g = 1, r l = 10 k , c l = 100 pf 20mv/div 20mv/div 1s/div 09412-049 g = 10 25c 175c 210c 225c figure 45 . small signal response, g = 1 0, r l = 10 k , c l = 100 pf
AD8229 rev. 0 | page 15 of 24 25 c 17 5 c 21 0 c 22 5 c g = 100 2 s/div 20mv/div 09412-094 figure 46 . small signal response, g = 1 00 , r l = 10 k , c l = 100 pf g = 1000 10 s/div 20mv/div 25 c 17 5 c 21 0 c 22 5 c 09412-095 figure 47 . small sign al response, g = 1 000 , r l = 10 k , c l = 100 pf g = 10 1 s/div 50mv/div no load c l = 100pf c l = 147pf 09412-093 figure 48 . small signal response with various capacitive loads , g = 1, r l = infinity 0 200 400 600 800 1000 1200 1400 2 4 6 8 10 12 14 16 18 20 settling time (ns) ste p size (v) settled to 0.001% settled to 0.01% 09412-092 figure 49 . settling time vs. step size, g = 1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequenc y (hz) no load 2k load 600 load g = 1, second harmonic v out = 10v p-p 09412-096 figure 50 . second harmonic distortion vs. frequency, g = 1 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequenc y (hz) no load 2k load 600 load g = 1, third harmonic v out = 10v p-p 09412-097 figure 51 . third harmonic distortion vs. frequency, g = 1
AD8229 rev. 0 | page 16 of 24 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequency(hz) no load 2k load 600 load g = 1000, second harmonic v out = 10v p-p 09412-098 figure 52 . second harmonic distortion vs. frequency, g = 1000 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k amplitude (percentage of fundamental) frequenc y (hz) no load 2k load 600 load g = 1000, third harmonic v out = 10v p-p 09412-099 figur e 53 . third harmonic distortion vs. frequency, g = 1000 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1k 10k 100k thd (%) frequenc y (hz) gain = 1 gain = 100 v out = 10v p-p r l 2k gain = 10 gain = 1000 09412-100 figure 54 . thd vs. frequency
AD8229 rev. 0 | page 17 of 24 theory of operation a3 a1 a2 q2 q1 c1 c2 +in ?in +v s ?v s +v s ?v s +v s ?v s r3 5k? r4 5k? r5 5k? rg? +v s ?v s output ref node 1 node 2 i b compens a tion i b compens a tion r g v b i i +v s ?v s +v s ?v s r6 5k? rg+ r2 3k? r1 3k ? 09412-058 figure 55 . simplified schemati c architecture the AD8229 is based on the classic 3 - op - amp topology. this topology has two stages: a preamplifier to provide differential amplification followed by a difference amplifier that removes the common - mode voltage and provides additional amplifica - tion. figure 55 shows a simplified schematic of the ad822 9. the first stage works as follows. to keep its two inputs matched, amplifier a1 must keep the collector of q1 at a constant voltage. it does this by forcing rg ? to be a precise diode drop from C in. similarly , a2 forces rg+ to be a constant diode drop from +in. therefore, a replica of the differential input voltage is placed across the gain setting resistor, r g . the current that flows through this resistance must also flow through the r1 and r2 resistors, creating a gained differential signal between the a2 and a1 outputs. the second stage is a g = 1 difference amplifier, composed of a mplifier a3 and the r3 through r6 resistors . this stage removes the common - mode signal from the amplified differential signal. the transfer function of the AD8229 is v out = g ( v in+ ? v in? ) + v ref where: g r g k 6 1 + = gain selection placing a resistor across the r g terminals sets the gain of the AD8229 , which can be calculated by referring to table 5 or by using the following gain eq u ation: 1 k 6 ? = g r g table 5 . gains achieved sing 1 resistors 1% standard table value of r g ( ?) calculated gain 6.04 k 1.99 3 1.5 k 5.000 665 10. 02 316 19.99 121 50.59 60.4 100.34 30.1 200.34 12.1 496.9 6.04 994.4 3.01 1994.355 the AD8229 defaults to g = 1 when no gain resistor is used. the tolerance and gain drift of the r g resist or should be added to the AD8229 s specifications to determine the total gain accu - racy of the system. w hen the gain resistor is not used , g ain error and gain drift are minimal . r g p ower dissipation the AD8229 duplicate s the differential voltage across its inputs onto the r g resistor. the r g resistor size should be chosen to handle the expected power dissipation. reference terminal the output voltage of the AD8229 is developed with respect to the potential on the reference terminal. this is useful when the output signal must be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level - shi ft t he output so that the AD8229 can drive a single - supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.3 v.
AD8229 rev. 0 | page 18 of 24 for best performance, source impedance to the ref terminal should be kept well be low 1 ? . as shown in figure 55 , the reference term inal, ref, is at one end of a 5 k resistor. additional imped ance at the ref terminal adds to this 5 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be c alculat ed as follows: 2(5 k + r ref )/(10 k + r ref ) only the positive s ignal path is amplified; the negative path is unaffected. this uneven amplification degrades cmrr. incorrect v correct AD8229 op1177 + ? v ref AD8229 ref 09412-059 figure 56 . driving the reference pin input voltage range figure 10 through fig ure 15 show the allowable common - mode input voltage ranges for various output voltages and supply voltages. the 3 - op - amp architecture of the AD8229 applies gain in the first stage before removing common - mode voltage with the difference amplifier stage. in ternal nodes between the first and second stages (node 1 and node 2 in figure 55 ) experience a combination of a gained signal, a common - mode signal, and a diode drop. this combined signal can be limited by the volta ge supplies even when the individual input and output signals are not limited. layout to ensure optimum performance of the ad822 9 at the pcb level, care must be taken in the design of the board layout. the pins of the ad822 9 are arranged in a logical mann er to aid in this task. 8 7 6 5 1 2 3 4 ?in r g r g +v s v out ref ?v s +in t op view (not to scale) AD8229 09412-060 figure 57 . pinout diagram common - mode rejection ratio over frequency poor layout can cause some of the common - mode signals to be converted to differential signal s before reaching the in - amp. such conversi ons occur when one input path has a frequency response that is different from the other. to keep cmrr over frequency high, the input source impedance and capacitance of each path should be closely matched. additional source resis - tance in the input path (f or example, for input protection) should be placed close to the in - amp inputs, which minimizes their interaction with parasitic capacitance from the pcb traces. parasitic capacitance at the gain setting pins can also affect cmrr over frequency . if the boar d design has a component at the gain setting pins (for example, a switch or jumper), the component should be chosen so that the parasitic capacitance is as small as possible. power supplies a stable dc voltage should be used to power the instrumentation am plifier. noise on the supply pi ns can adversely affect perfor - m ance. see the psrr performance curves in figur e 19 and figure 20 for more information. a 0.1 f capacitor should be placed as close as po ssible to each supply pin . as shown in figure 58 , a 10 f tantalum capacitor can be used fa rther away from the part. in most cases, it can be shared by other precision integrated circuits. AD8229 +v s +in ?in load r g ref 0.1 f 10 f 0.1 f 10 f ?v s v out 09412-061 figure 58 . sup ply decoupling, ref, and output referred to local ground reference pin the output voltage of the AD8229 is developed with respect to the potential on the reference terminal. care should be taken to tie ref to the appropriate local ground.
AD8229 rev. 0 | page 19 of 24 input bias curr ent return path the input bias current of the ad822 9 must have a return path to ground. when using a floating source without a current return path , such as a thermocouple, a current return path should be created, as shown in figure 59 . thermocouple +v s ref ?v s AD8229 capacitively coupled +v s ref c c ?v s AD8229 transformer +v s ref ?v s AD8229 incorrect capacitively coupled +v s ref c r r c ?v s AD8229 1 f high-pass = 2rc thermocouple +v s ref ?v s 10m ? AD8229 transformer +v s ref ?v s AD8229 correct 09412-062 figure 59 . creating an input bias current return path input protection the inputs to the AD8229 should be kept within the ratings stated in the absolute maximum ratings section of t his data sheet. if this cannot be done, protection circuitry can be added in front of the AD8229 to limit the current into the inputs to a maximum current , i max . input voltages b eyond the rails if voltages beyond the rails are expected , an external resisto r should be used in series with each input to limit current during overload conditions. the limiting resistor at the input can be computed from max supply in protect i v v r | | ? noise - sensitive applications may require a lower protection resistance. l ow leakage d iod e clamps, such as the bav199 , can be used at the inputs to shunt curr ent away from the AD8229 inputs and therefore allow smaller protection resistor values. to ensure current flows primarily through the external protection diodes, place a small value resis tor, such as a 33 , between the diodes and the AD8229. simple method low noise method +v s AD8229 r protect r protect ?v s i v in+ + ? v in? + ? 09412-066 +v s +v s AD8229 r protect 33? 33? r protect ?v s ?v s i v in+ + ? v in? + ? +v s ?v s figure 60 . protection for voltages bey o nd the rails large differential input voltage at high gain if large differential voltages at high gain are expected, an external resi stor should be used in series with each input to limit current during overload conditions. the limiting resistor at each input can be computed from ? ? ? ? ? ? ? ? ? ? g max diff protect r i v v r 1 | | 2 1 noise - sensitive applications may require a lower protection resistance. l ow leakage d iode clamps, such as the bav199 , can be used across the inputs to shunt current away from the AD8229 inputs and therefore allow smaller protection resistor values. 09412-067 AD8229 r protect r protect i v diff + ? AD8229 r protect r protect i v diff + ? simple method low noise method figure 61 . protection for large differential voltages i max the m aximum current into the AD8229 inputs, i max , depends both on time and temperature. at room temperature, the part can withstand a cu rrent of 10 ma for at least a day . this time is cumulative over the lif e of the part. at 210 c, current should be limited to 2 m a for the same period of time. the part can withstand 5 ma at 210c for an hour, cumulat ive over the life of the part. radio frequency interference (rfi) rf rectification is often a problem when amplifiers are used in applications that hav e strong rf si gnals. the disturbance can appear as a small dc offset voltage. high frequency signals can be filtered with a low - pass rc network placed at the input of the instrumentation amplifier, as shown in figure 62 . the filter limits the in put signal bandwidth, according to the following relationship: ) 2 ( 2 1 c d diff c c r uency filterfreq + =
AD8229 rev. 0 | page 20 of 24 c cm rc uency filterfreq 2 1 = where c d 10 c c . r r AD8229 +v s +in ?in 0.1f 10f 10f 0.1f ref v out ?v s r g c d 10nf c c 1nf c c 1nf 4.02k ? 4.02k ? 09412-063 figure 62 . rfi suppression c d affects the difference signal , and c c affects the common - mode signal. values of r and c c should be chosen to minimize rfi. a mismatch between r c c at the positive input and r c c at the negative input degrades the cmrr of the ad822 9 . by using a value of c d one magnitude larger than c c , the effect of the mis - match is reduc e d, and performance is improved. resistors add noise ; therefore, t he resistor and capacitor values chosen depend on the desired tradeoff between noise, input impedance at high frequencies, and rfi immunity. the resistors used for the rfi filter can be the same as those used for input protection. calculating the noise of the in put stage r2 r g r1 sensor AD8229 09412-064 figure 63 . AD8229 with s ource resistance from sensor and protection r esistors the total noise of the amplifier front end depe nds on much more than the 1 nv/ hz headline specification of this data sheet . the total noise is dependent on three main factors: the source resistance, the voltage noise of the instrumentation amplifier, and the current noise of the instrumentation amplifier. in the following cal culations, noise is referred to the input (rti). in other words , everything is calculated as if it appear ed at the amplifier input. to calculate the noise referred to the amplifier output (rto), simply multiple the rti noise by the gain of the instrumentat ion amplifier. source resistance noise any sens or connected to the AD8229 has some output resistance. there may also be resistance placed in series with inputs for protection from either overvoltage or radio frequency inter - ference. this combined resistanc e is labeled r1 and r2 in figure 63. any resistor , no matter how well made, has a minimum level of noise. this noise is proportional to the square root of the resistor value. at room temperature , the value is appro ximately equa l to 4 nv/ hz (r esistor v alue in k ). for example, assuming that the combined sensor and protection resistance on the positive input is 4 k an d on the negative input is 1 k , the total noise from the resistance is 2 2 ) 1 4 ( ) 4 4 ( + = 16 64 + = 8.9 nv/ hz voltage noise of the instrumentation amplifier the voltage noise of the instrumentation amplifier is calculated using three parameters: the part input noise, output noise, and the rg resistor noise. it is calcu lated as follows : total voltage n oise = 2 2 2 ) ( ) ( ) / ( resistor rg of noise noise input g noise output + + for example , for a gain of 1 0 0 , the gain resistor is 60.4 . there - fore, the voltage noise of the in - amp is 2 2 2 ) 0604 . 0 4 ( 1 ) 100 / 43 ( + + = 1.5 nv/ hz current noise of the instrumentation amplifier current noise is calculated by multiplying the source re sistance by the cur rent noise. for example , i f the r1 source resistance in figure 63 is 4 k , and the r2 source resistance is 1 k , t he total effect from the current noise is calculated as follows: ) ) 5 . 1 1 ( ) 5 . 1 4 (( 2 2 + = 6.2 nv/ hz total noise calculation to d e te rmine the total noise of the in - amp, referred to input, combine the source re sistance noise, voltage noise, and current noise contribution by the sum of squares method. for example, i f the r1 source resistance in figure 63 is 4 k , the r2 source resistance is 1 k , and the gain of the in - amps is 100, the total noise, referred to input , is ) 2 . 6 5 . 1 9 . 8 2 2 2 + + = 1 1 .0 nv/ hz
AD8229 rev. 0 | page 21 of 24 outline dimensions 07-08- 2010-b 0.054 nom 0.032 nom 0.130 nom 8 5 1 4 0 . 3 2 0 0 . 3 1 0 0 . 3 0 0 0 . 2 9 8 0 . 2 9 0 0 . 2 8 2 0 . 5 2 8 0 . 5 2 0 0 . 5 1 2 0 . 3 0 5 0 . 3 0 0 0 . 2 9 5 0 . 1 2 5 0 . 1 1 0 0 . 0 9 5 0 . 3 1 0 0 . 3 0 0 0 . 2 9 0 0 . 1 0 5 0 . 0 9 5 0 . 0 8 5 0 . 0 2 0 0 . 0 1 8 0 . 0 1 6 0 . 1 0 5 0 . 1 0 0 0 . 0 9 5 0 . 0 4 5 0 . 0 3 5 0 . 0 2 5 0 . 0 1 1 0 . 0 1 0 0 . 0 0 9 0 . 0 1 1 0 . 0 1 0 0 . 0 0 9 index mark seating plane 0 . 1 7 5 nom figure 64 . 8 - lead side - brazed ceramic dual in - line package [sbdip] (d - 8- 1) ) dimensions s hown in inches ordering guide model 1 temperature range package description package option AD8229hdz ?40c to +210 c ceramic dual in - line package [sbdip] d -8 -1 1 z = rohs compliant part.
AD8229 rev. 0 | page 22 of 24 notes
AD8229 rev. 0 | page 23 of 24 notes
AD8229 rev. 0 | page 24 of 24 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09412-0-1/11(0)

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